ASIC
Intel 16nm<br>SoC Tapeout
Architectural exploration and system-level evaluation of a 500 MHz RISC-V DSP SoC fabricated in Intel 16 nm
3-Stage<br>RISC-V CPU
Physically realistic ASIC implementation with synchronous SRAMs and private L1 cache
Architectural exploration and system-level evaluation of a 500 MHz RISC-V DSP SoC fabricated in Intel 16 nm
Physically realistic ASIC implementation with synchronous SRAMs and private L1 cache