ASIC

  • 1st May 2025
  • /projects/tapeout/dsp25_block_diagram.png

Intel 16nm<br>SoC Tapeout

Architectural exploration and system-level evaluation of a 500 MHz RISC-V DSP SoC fabricated in Intel 16 nm

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  • 1st December 2024
  • projects/asic_aces/thumbnail2.png

3-Stage<br>RISC-V CPU

Physically realistic ASIC implementation with synchronous SRAMs and private L1 cache

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