μISA-16
Microcoded CPU

Overview

μISA-16 is an in-progress personal project exploring verification-driven CPU design using a deliberately minimal instruction set and a microcoded execution model.

The primary goal of the project is to develop proficiency with SystemVerilog and SystemVerilog Assertions (SVA) in a setting where architectural invariants, instruction semantics, and control flow can be stated precisely and verified formally. Rather than optimizing for performance or feature completeness, the design emphasizes clarity of specification and explicit architectural guarantees.

The CPU executes one instruction at a time using a microcode ROM with explicit instruction commit semantics. This execution model is intentionally chosen to make assertion-based verification a guarantor of CPU behavior and control flow.

Development is currently ongoing. Design notes, ISA documentation, and verification status are being maintained publicly in my GitHub repository.

At a Glance

  • Architecture: 16-bit microcoded CPU.
  • Execution model: Multi-cycle, no pipeline.
  • Registers: 8 GPRs (R0 hardwired to zero, R7 as stack pointer).
  • Instruction set: Minimal fixed-length ISA, defined for precise semantic specification.
  • Verification focus: SystemVerilog Assertions, lightweight UVM-style harness, directed and randomized testing.
  • Status: In progress.

Technical Focus

This project is intentionally scoped to emphasize verification concepts over implementation complexity, including:

  • Bit-accurate ISA and instruction encoding design, with a formally specified architectural state.
  • Explicit architectural commit semantics separating architectural guarantees from microarchitectural detail.
  • Assertion-based verification of:
    • PC, register file, and architectural state invariants.
    • Illegal instruction detection and defined trap behavior.
    • Instruction-level semantic correctness across multi-cycle execution.
    • Microcode forward progress and bounded termination.
  • Clear separation between architectural correctness properties and software conventions or testbench assumptions.

The project also serves as a contrast to prior pipelined and tapeout-oriented work by prioritizing control transparency, formal reasoning, and correctness guarantees over throughput or timing closure.

Current Status

Work in progress includes:

  • Finalizing ISA documentation and encoding details.
  • Implementing the microcoded control engine.
  • Incrementally adding architectural and control-level SVAs, starting with safety invariants and expanding toward instruction-level correctness.
  • Building a lightweight verification harness with basic coverage. The design and verification strategy are evolving iteratively as assertions are added and refined.

Repository

All development, documentation, and verification artifacts are publicly available on GitHub at https://github.com/noah-CAL/microISA-16/.

Follow the repository for ongoing progress and design notes.