ASIC CPU
The final project for my Integrated Circuits and Digital Design class (EECS 151) had us build, design, and implement a 3-stage pipelined RISC-V CPU in Verilog. The project writeup is coming soon!
The final project for my Integrated Circuits and Digital Design class (EECS 151) had us build, design, and implement a 3-stage pipelined RISC-V CPU in Verilog. The project writeup is coming soon!