Projects
I am working on writeups for all my projects! Stay tuned and check out my CV for more.
Intel 16nm
SoC Tapeout
Architectural exploration and system-level evaluation of a 500 MHz RISC-V DSP SoC fabricated in Intel 16 nm
3-Stage
RISC-V CPU
Physically realistic ASIC implementation with synchronous SRAMs and private L1 cache
μISA-16
Microcoded CPU
(In Progress) Verification-driven design of a minimal 16-bit microcoded CPU using SystemVerilog Assertions