/projects/tapeout/dsp25_block_diagram.png

Intel 16nm
SoC Tapeout

Architectural exploration and system-level evaluation of a 500 MHz RISC-V DSP SoC fabricated in Intel 16 nm
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3-Stage
RISC-V CPU

Physically realistic ASIC implementation with synchronous SRAMs and private L1 cache
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μISA-16
Microcoded CPU

(In Progress) Verification-driven design of a minimal 16-bit microcoded CPU using SystemVerilog Assertions

Latest posts

  • 21st April 2025
  • /blog/one-bit-challenge/thumbnail.svg
  • 26th March 2025
  • /blog/one-bit-challenge/thumbnail.svg

Binary Modification: Part 1

ELFBinary ExploitationGNU Binutils

Fun challenge to get familiar with ELF files, instruction encoding, and binary modification. Can you solve it?

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